an0 11 july 2000 1 a novel, cost - effective technique for converting vrm8.x vid to vrm9.0 compatible vid abstract since aic1569a has been designed to meet the pentium ii processor, the equipped voltage level range is from 3.5v to 1.3v. as the trend of new generatio n cpu core voltage decreasing goes on, the only and also major problem of vid setting is the mismatch with (the vid setting can?t meet) the requirement of the (these) new processors. however, (somehow,) this problem can be solved by adding a simple circuit externally. due to the overlap voltage range between socket a cpu and that provided by aic1569a, this method provides a cost - effective solution for socket a cpu. vid configuration vid pins are used to set the voltage reference for cpu core voltage. this is accomplished by a build - in digital - to - analog converter in aic1569a. there are 5 vid pins named from vid0 to vid4 comprising 32 selections of voltage level. on the other hand, vid definition of socket a cpu (amd thunderbird) also is configured with 5 pin s, named vidx (x=0~4), to define the voltage range from 1.85v to 1.1v. the following table shows both the aic1569a and thunderbird cpu voltage levels versus vid setting. v core (vid4=0) v core (vid4=1) vid[3:0] socket a aic1569a keep socket a aic1569a re define 0000 1.850 2.05 2.050 1.450 3.5 2.075 0001 1.825 2.00 2.000 1.425 3.4 2.025 0010 1.800 1.95 1.950 1.400 3.3 1.975 0011 1.775 1.90 1.900 1.375 3.2 1.925 0100 1.750 1.85 1.850 1.350 3.1 1.875 0101 1.725 1.80 1.800 1.325 3.0 1.825 0110 1.700 1.7 5 1.750 1.300 2.9 1.775 0111 1.675 1.70 1.700 1.275 2.8 1.725 1000 1.650 1.65 1.650 1.250 2.7 1.675 1001 1.625 1.60 1.600 1.225 2.6 1.625 1010 1.600 1.55 1.550 1.200 2.5 1.575 1011 1.575 1.50 1.500 1.175 2.4 1.525 1100 1.550 1.45 1.450 1.150 2.3 1.47 5 1101 1.525 1.40 1.400 1.125 2.2 1.425 1110 1.500 1.35 1.350 1.100 2.1 1.375 1111 1.475 1.30 1.300 no cpu 0v 1.325 by comparing the voltage values in the table, 2 problems are found in the vid mismatch condition. first, voltage range of aic1569a can not cover the range of socket a cpu, as mentioned above. second,
an0 11 2 for socket a cpu, the voltage step is 25mv within all range. however, in aic1569a, voltage step is 100mv within the range from 3.5v to 2.1v and 50mv from 2.1v to 1.3v. you may have noticed t hat, the difference between 100mv step and 50mv step can be categorized by the vid4 value. besides, the range of 3.5v~2.1v is not used for socket a cpu. thus we can redefine the vid4 pin as a ?plus 25mv? function, used within the range of 2.1v to 1.3v. the gray area in the above table is the redefined vid voltage level. circuit modification how do we apply this redefined vid voltage to practical circuit? the principle is quite simple. since the vid4 pin of aic1569a is no longer used, it is connected to gro und to keep the reference voltage in the range from 2.05v to 1.3v. the ?plus 25mv? function is controlled by the other on/off pin, named vid5. the status of vid5 controls an npn transistor to enable a resistor that connects between vfb and gnd to modify th e feedback voltage. two circuits are shown in the following figure to convey this idea. vfb d/a vid4 vid[0:3] z1 comp vcc vcore qs 2n2222 r2 3k r1 200k r3 1k vid5 aic1569a ea suggested circuit worst choice second choice in the above figure, ?suggested circuit? is a little complicated but much more reliable than the ?second choice?. r2 is the original re sistor used with z1 to accomplish the compensation network. adding an r1 resistor effectively divides the feedback voltage. this also causes the compensator to increase the output voltage. vid5, grounding of r1 depends on the control circuit which is compr ised of r3 and qs. as vid5 open, qs is turned off. r1 would not consume any current, voltage on vfb equal to vcore. and when vid5 closed, qs is turned on. voltage on vfb is then no longer vcore, it gets a smaller vcore than actual
an0 11 3 output voltage. the ?wors t choice? is applied by the same principle as the ?suggested circuit?, but may induce much more noise and interference while vid5 is open. the ?second choice may be the best choice while considering the trade off between cost and noise problem. the advant age of this circuit eliminate the point may induce noise while converter operating. one consideration may be its disadvantage is the switch is not suggested to change while converter operation, the reason is noise may be introduce during the time changing the switch position. with this point of view, change switch position of ?suggested circuit? can be proceed any time, no matter the converter is operating or not. control circuit design and verification the principle now is very clear, using vid5 to enable the divide circuit. the divided voltage can be calculated by the following equation: core fb v r2 r1 r1 v + = by the linear equation shown above, the relation between vfb and vcore is proportional, not offset. this means we have to choose a proper value o f divide resistor (r1) to match the 25mv offset at different reference voltage as possible as we can. usually, the r2 value is a parameter decided in compensator design. this simplifies the design of divider. let?s assume r2 is designed to be 3ko, then a mid point is chosen in the vid voltage range. for example, the mid point is 1.7v, and the value of r1 can be calculated as follows. 204k o (3k/0.025) 1.7 r1 0.025 1.7 1.7 r2 r1 r1 = = t + = + thus, r2 is chosen to be 200ko, as we saw in the above schematics. on the other hand, v oltage offset under different vid set can also be calculated. the following table shows the calculated value and measured value of the new vid modification circuit.
an0 11 4 defined voltage (v) measured voltage (v) deviation (mv) voltage rise (mv) vid[3:0] vid 5 off vid5 on vid5 off vid5 on vid5 off vid5 on calculated measured 0000 2.050 2.075 2.052 2.083 2 8 30 33 0001 2.000 2.025 2.000 2.031 0 6 30 31 0010 1.950 1.975 1.952 1.981 2 6 29 29 0011 1.900 1.925 1.900 1.929 0 4 28 29 0100 1.850 1.875 1.852 1 .880 2 5 27 30 0101 1.800 1.825 1.800 1.827 0 2 27 27 0110 1.750 1.775 1.752 1.778 2 3 26 28 0111 1.700 1.725 1.702 1.727 2 2 25 27 1000 1.650 1.675 1.652 1.677 2 2 24 27 1001 1.600 1.625 1.600 1.624 0 - 1 24 24 1010 1.550 1.575 1.552 1.575 2 0 23 25 1011 1.500 1.525 1.501 1.523 1 - 2 22 23 1100 1.450 1.475 1.452 1.474 2 - 1 21 24 1101 1.400 1.425 1.400 1.421 0 - 4 21 21 1110 1.350 1.375 1.352 1.372 2 - 3 20 22 1111 1.300 1.325 1.300 1.320 0 - 5 19 20 the above table contains the designed and measur ed data that is tested at no load condition. first column is the set of vid pins (note vid4 is always connected to ground as shown in above schematics). the second and third columns are the redefined voltage levels. the column with ?vid5 on? is always 25mv higher than the column with ?vid5 off?. the fourth and fifth columns are the authentic data measured with vid5 off and on, respectively. the sixth and seventh columns show the calculated data of deviation voltage between setting and measured voltage. obvi ously the voltage variation with vid5 on turns more dramatic than off, especially at the larger and smaller voltage setting. the last 2 columns are the data from the circuit?s point of view to see the differences between the r2 design and implementation. a nd the result turns out to be almost the same. conclusion from the test result, some conclusions are made: 1. the redefined vid table can be categorized into 2 parts, the original part of vid4=0, voltage level range is from 2.05v to 1.3v in 50mv step. the ot her part is an extension from the first part with additional 25mv, which is controlled by a new vid5 bit. hence, the total provided voltage range is from 2.075v to 1.3v in 25mv step (32 voltage level totally). 2. the extended vid setting can provide the same voltage step as the needs of the socket a cpu, which is 25mv. however, during the implementation the voltage step is not so accurate. the highest voltage defined in socket a cpu is 1.85v. that means there are 9 voltage levels (from 2.075v to 1.875v), that are not used. on the other hand, this derived vid setting can only provide the voltage of 1.3v. in other words, the
an0 11 5 range of 8 voltage levels from 1.275v to 1.1v is not provided to the socket a cpu. 3. thus, the valid range provided by the redefined vid table is 1.85v to 1.3v, 23 voltage levels totally. besides, the ?no cpu? defined in socket a cpu is also not provided. 4. the typical vcore voltage for socket a cpu is 1.7v. therefore, this new derived vid can meet the requirement with no doubt. for the sleeping mode, typically vcore voltage is 1.3v, also can be provided, but with less flexibility. 5. the voltage level with vid5=1, that is, adding 25mv, had worse voltage deviation than vid5=0, yet still acceptable. the worst case is about 8mv higher at 2.075v and 5mv lower at 1.325v. these values may vary according to case design. 6. actually, for more cost - effective method, this circuit can simply be further simplified by using r1 and vid5 as the ?second choice? and ?worse choice? shown above. this can also achieve the same result but may induce much more noise than original design when the vid5 is open. please note that lots of care should be taken when implementing this application. cost difference between ?second choice? and ?worst choice? is only a pin. as the new g eneration cpu?s performance progressing rapidly, the requirement of power supply specification also challenges the power electronics technology. although multi - phase converter can meet the power requirement for cpu of the next few generations, high cost an d complex technology is the price that has to pay at this moment. this article introduces a cost effectively solution for those users who are not ready to go for the multi - phase technology, but have involved with products of k7 socket a cpu. by adding a si mple circuit (2 resistor, 1 npn transistor), the old design can then meet the vid requirement of socket a cpu. it?s simple, easy and cost - effective.
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